Deep-submicron scaling required for VLSI systems dominates design considerations in the microelectronics industry. As the gate electrode length is scaled down, the source and drain junctions must be scaled down accordingly to suppress the so-called short channel effects (SCE) that degrade performance of miniaturized devices. A major problem related to complementary metal oxide silicon (CMOS) scaling is the undesirable increase in parasitic resistance. As the source/drain junction depth and polycrystalline silicon line width are scaled into the deep-submicron range, parasitic series resistances of the source/drain diffusion layers and polysilicon gate electrodes increase. A conventional approach to the increase in parasitic series resistances of the source/drain diffusion layers and the polysilicon gate electrodes involves salicide technology which comprises forming a layer of metal silicide on the source/drain regions and gate electrode.
Conventional salicide technology for reducing parasitic series resistance has proven problematic, particularly as design rules plunge into the deep-submicron range, such as about 0.18 microns and under. For example, agglomeration causes silicide to have high sheet resistance.
It can be appreciated from the geometry of a MOS device that smaller device sizes, in particular a shorter distance between the source and drain, will allow the conducting channel between the source and drain to form more rapidly and allow the device to operate at higher switching speeds. As the device dimensions are reduced to achieve higher packing densities and improved performance, the junction depth needs to be scaled in proportion to the junction length. However, the formation of silicide consumes crystalline silicon from the underlying semiconductor substrate. When the junction depth is significantly smaller than the thickness of the silicide, the thickness variation of the silicide caused by process variations may be greater than the junction depth, making the junction depth very hard to control.
Various approaches have been taken to solve the above-mentioned problems. In a first attempt, a thin layer of Cobalt-tungsten alloy is selectively deposited on the source/drain (S/D) silicon layer. The Cobalt-tungsten alloy layer acts as a silicide barrier layer. A Nickel or Cobalt layer is formed on the Cobalt-tungsten alloy layer. With the presence of the silicide barrier layer, the silicide formation is hampered at the interface between the S/D silicon and the silicide barrier layer, and there is little consumption of silicon from the underlying substrate or gate electrode. Therefore, the ultra-shallow junction can be formed without encountering junction leakage. However, the Cobalt-tungsten alloy has high resistivity, which degrades the overall junction performance. Additionally, It is not easy to control tungsten concentration in the Cobalt-tungsten alloy.
In another approach, a Cobalt layer doped with phosphorous is blanket deposited on the S/D silicon layer. A silicide control layer of titanium is formed on the doped Cobalt layer. An annealing or rapid thermal processing process is performed. The titanium layer partially alloys with the previously deposited Cobalt layer in the annealing step. The alloying of the titanium and Cobalt binds up or getters a portion of the deposited Cobalt. The titanium-Cobalt alloy does not readily react with the underlying silicon to form a silicide. This helps to control the thickness of silicide formed in a subsequent salicide process. The un-silicided Cobalt reacts with the S/D silicon to form a Cobalt silicide. The remaining titanium and titanium-Cobalt alloy, including those over the S/D regions and over other regions, are then removed with a wet etching process. Through this conventional embodiment, a low resistance contact is formed and the leakage is well controlled. However, extra steps have to be taken to remove the titanium and titanium-Cobalt alloy.
Accordingly, there exists a need for alternative technology that enables a reduction in parasitic series resistance without causing junction leakage. There exists a particular need for simplified methodology for forming low resistance contacts in semiconductor devices with increased reliability, reduced junction leakage, and high transistor speed.